System Verilog-VMM links
Posted by Subash | 3:46 PM
[5] Comments
These days I am working on System Verilog/VMM (for those lucky one who don't know what these are, System Verilog is a Hardware Verification Language which is used for verifying complex multi-million gates digital designs, and VMM is a verification methodology for the same):-
Presentations:-
- SV - Design
- SV - Testbench
- SV - Assertion
- SV - DPI
- SV - Tranings (133 slides)
- And many more such presentations :)
Labels: Presentations, System Verilog, Verification
