My Tech Blog

These days I am working on System Verilog/VMM (for those lucky one who don't know what these are, System Verilog is a Hardware Verification Language which is used for verifying complex multi-million gates digital designs, and VMM is a verification methodology for the same):- Presentations:-

• SV - Design
• SV - Testbench
• SV - Assertion
• SV - DPI
• SV - Tranings (133 slides)
• And many more such presentations :)

Labels: Presentations, System Verilog, Verification

Comments (5)

1.  Anonymous said:  
   12:03 PM
   the link to prolog page is not working. pls change the file extension. It is given as "htl".
   
   
   -- Bishwa
2.  mstsvetk said:  
   11:17 PM
   IMHO the best source for SV learning (don't HA-HA!) is the SV standard (2009 edition completly perfect - it combines verilog and SV now). Execptional standard - it's written like perfect tutorial.
3.  Subash said:  
   11:25 PM
   @mstsvetk, You mean the 3.1 LRM, Its good, but for beginners, these links are better. I am telling this from my personal experience.
   
   @ mstsvetk, Вы имеете в виду 3,1 LRM, добрые, но и для начинающих, эти ссылки лучше. Я говорю от этого моего личного опыта.
4.  Anonymous said:  
   3:23 PM
   hii...this is prima from bangladesh. im doing my undergrade thesis on verilog. can u help us by providing some topics on this.
   contact me at verilogthesis@ymail.com
5.  verilogfreak said:  
   8:33 PM
   Hi,
   
   subash, I have onsite interview with Mentor graphics for Associate Rotation Engineer - DFT, for this job i need to be proficient with perl, system verilog, linux, c++, synopsys and dft. could you please suggest some questions based on this topics,you can ask me considering your my interviewer, i will be very helpful for that. email me at venky_chitos@yahoo.co.in

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